1. Field of the Invention
The present invention pertains to liquid crystal display (LCD) drivers, and in particular pertains to a signal processing system which will compensate for processing (speed) differences between driver chips used to drive an active matrix LCD display.
2. Description of the Prior Art
Military and commercial applications for flat panel, active matrix LCD's are growing. There is a need for "next generation" IC's which can take full advantage of the capabilities of current and upcoming active matrix displays by providing extreme image accuracy with a large number of gray levels. Space is a primary concern in applications using flat panel displays.
Active matrix displays can provide advantages over conventional LCD's in the areas of viewing angle, response time and information content. Military and commercial applications such as cockpit displays, mapping displays and imaging systems can utilize these features to create extremely accurate image reproductions. A new generation of complex mixed signal driver chips are required to implement these systems.
Current system architectures for LCD drivers employ both row and column driver IC's. The column driver is a high speed chip having responsibility for accurate generation of the gray shade voltage levels. These IC's need to be fast, handle large voltages, have a multitude of outputs, provide low offset error, contain tens of thousands of transistors, and yet minimize power. These conflicting design issues require careful analysis in the light of current IC technology.
In previous active matrix driver chips, offset error was not an issue due to the relatively slow speed of the chips and the low number of gray scales provided. In a 256 gray level display however, the offset error at the outputs is a critical electrical issue affecting system performance. Offset error will appear as a shading problem on the display and may cause unwanted or fuzzy image features. Many "track and hold" applications strive to minimize offset between outputs but may allow for a system tuning process to adjust for a common offset. Applications such as displays however, use multiple IC's in the same system. Individual tuning of 30 or more IC's is undesirable. The offsets must not only match on chip, but from chip to chip as well. This presents a significant design problem due to IC process variations. The contributors to output error include: 1. leakage on the hold capacitor, 2. amplifier DC offset error, 3. switch capacitor error and 4. aperture error (jitter, uncertainty and delay).
Aperture delay is a measure of the delay between the external clock edge and the internal edge which actually causes the voltage to be held. This is a transient case and is one of the largest contributors to the overall error because all chips in the system need to have identical aperture delay.
The present invention provides a speed compensation circuit which solves the aperture delay problem. The compensation circuit is designed to equalize the delay for all chips, under all processing conditions. The effect is to add delay to the faster processes.